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ICS932S208 idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 programmable timing control hub tm for next gen p4 tm processor 1 datasheet pin configuration recommended application: ck409b clock, intel yellow cover part, server applications output features: ? 4 - 0.7v current-mode differential cpu pairs 1 - 0.7v current-mode differential src pair 7 - pci (33mhz) 3 - pciclk_f, (33mhz) free-running 1 - usb, 48mhz 1 - dot, 48mhz 2 - ref, 14.318mhz 4 - 3v66, 66.66mhz 1 - vch/3v66, selectable 48mhz or 66mhz key specifications: cpu/src outputs cycle-cycle jitter < 125ps 3v66 outputs cycle-cycle jitter < 250ps pci outputs cycle-cycle jitter < 250ps cpu outputs skew: < 100ps +/- 300ppm frequency accuracy on cpu & src clocks features/benefits: supports tight ppm accuracy clocks for serial-ata supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread supports cpu clks up to 400mhz in test mode uses external 14.318mhz crystal 56-pin ssop & tssop ref0 1 56 fs_b ref1 2 55 vdda vddref 3 54 gnda x1 4 53 gnd x2 5 52 iref gnd 6 51 fs_a pciclk_f0 7 50 cpuclkt3 pciclk_f1 8 49 cpuclkc3 pciclk_f2 9 48 vddcpu vddpci 10 47 cpuclkt2 gnd 11 46 cpuclkc2 pciclk0 12 45 gnd pciclk1 13 44 cpuclkt1 pciclk2 14 43 cpuclkc1 pciclk3 15 42 vddcpu vddpci 16 41 cpuclkt0 gnd 17 40 cpuclkc0 pciclk4 18 39 gnd pciclk5 19 38 srcclkt pciclk6 20 37 srcclkc pd# 21 36 vdd 3v66_0 22 35 vtt_pwrgd# 3v66_1 23 34 vdd48 vdd3v66 24 33 gnd gnd 25 32 48mhz_dot 3v66_2 26 31 48mhz_usb 3v66_3 27 30 sdata sclk 28 29 3v66_4/vch ICS932S208 functionality b6b5 fs_a fs_b cpu mhz src mhz 3v66 mhz pci mhz ref mhz u sb/dot mhz 0 0 100 100/200 66.66 33.33 14.318 48.00 0 mid ref/n 0 ref/n 1 ref/n 2 ref/n 3 ref/n 4 ref/n 5 0 1 200 100/200 66.66 33.33 14.318 48.00 1 0 133 100/200 66.66 33.33 14.318 48.00 1 1 166 100/200 66.66 33.33 14.318 48.00 1 mid hi-z hi-z hi-z hi-z hi-z hi-z 0 0 200 100/200 66.66 33.33 14.318 48.00 0 1 400 100/200 66.66 33.33 14.318 48.00 1 0 266 100/200 66.66 33.33 14.318 48.00 1 1 333 100/200 66.66 33.33 14.318 48.00 0 1
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 2 pin description pin # pin name pin type description 1 ref0 out 14.318 mhz reference clock. 2 ref1 out 14.318 mhz reference clock. 3 vddref pwr ref, xtal p ower su pp l y , nominal 3.3v 4x1 in cr y stal in p ut, nominall y 14.318mhz. 5 x2 out cr y stal out p ut, nominall y 14.318mhz 6 gnd pwr ground p in. 7 pciclk_f0 out free runnin g pci clock not affected b y pci_stop# . 8 pciclk_f1 out free runnin g pci clock not affected b y pci_stop# . 9 pciclk_f2 out free runnin g pci clock not affected b y pci_stop# . 10 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 11 gnd pwr ground p in. 12 pciclk0 out pci clock out p ut. 13 pciclk1 out pci clock out p ut. 14 pciclk2 out pci clock out p ut. 15 pciclk3 out pci clock out p ut. 16 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 17 gnd pwr ground p in. 18 pciclk4 out pci clock out p ut. 19 pciclk5 out pci clock out p ut. 20 pciclk6 out pci clock out p ut. 21 pd# in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 1.8ms. internal p ull-u p of 150k nominal. 22 3v66_0 out 3.3v 66.66mhz clock out p ut 23 3v66_1 out 3.3v 66.66mhz clock out p ut 24 vdd3v66 pwr power p in for the 3v66 clocks. 25 gnd pwr ground p in. 26 3v66_2 out 3.3v 66.66mhz clock out p ut 27 3v66_3 out 3.3v 66.66mhz clock out p ut 28 sclk in clock pin of i2c circuitry 5v tolerant
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 3 pin description (continued) pin # pin name pin type description 29 3v66_4/vch out 66.66mhz clock output for agp support. agp-pci should be aligned with a skew window tolerance of 500ps. vch is 48mhz clock out p ut for video controller hub. 30 sdata i/o data p in for i2c circuitr y 5v tolerant 31 48mhz_usb out 48mhz clock out p ut. 32 48mhz_dot out 48mhz clock out p ut. 33 gnd pwr ground p in. 34 vdd48 pwr power p in for the 48mhz out p ut.3.3v 35 vtt_pwrgd# in this 3.3v lvttl input is a leve l sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active low in p ut. 36 vdd pwr power su pp l y for src clocks, nominal 3.3v 37 srcclkc out complement clock of differential pair for s-ata support. +/- 300 pp m accurac y re q uired. 38 srcclkt out true clock of differential pair for s-ata support. +/- 300 pp m accurac y re q uired. 39 gnd pwr ground p in. 40 cpuclkc0 out complimentary clock of differential pai r cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 41 cpuclkt0 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 42 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 43 cpuclkc1 out complimentary clock of differential pai r cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 44 cpuclkt1 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 45 gnd pwr ground p in. 46 cpuclkc2 out complimentary clock of differential pai r cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 47 cpuclkt2 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 48 vddcpu pwr su pp l y for cpu clocks, 3.3v nominal 49 cpuclkc3 out complimentary clock of differential pai r cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 50 cpuclkt3 out true clock of differential pair cpu outputs. these are current mode out p uts. external resistors are re q uired for volta g e bias. 51 fs_a in fre q uenc y select p in, see fre q uenc y table for functionalit y 52 iref out this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 53 gnd pwr ground p in. 54 gnda pwr ground p in for core. 55 vdda pwr 3.3v p ower for the pll core. 56 fs_b in frequency select pin, see frequency table for functionality
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 4 general description block diagram power groups ICS932S208 follows intel ck409b yellow cover specification. this clock synthesizer provides a single chip solution for next generation p4 intel processors and intel chipsets. ICS932S208 is driven with a 14.318mhz crystal. it generates cpu outputs up to 200mhz. it also provides a tight ppm accuracy output for serial ata support. i ref pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic 48mhz, usb, dot x1 x2 xtal sdata sclk vtt_pwrgd# pd# fs_a fs_b control logic ref (1:0) cpuclkt (3:0) cpuclkc (3:0) srcclkt0 srcclkc0 3v66(4:0) pciclk (6:0) pciclkf (2:0) vdd gnd 3 6 xtal, ref 24 25 3v66 [0:3] 10,16 11,17 pciclk outputs 36 39 srcclk outputs 55 54 master clock, cpu analog 34 33 48mhz, pll n/a 53 iref 48, 42 45 cpuclk clocks description pin number
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 5 absolute maximum ratings symbol parameter min max units vdd_a 3.3v core supply voltage v dd + 0.5v v vdd_in 3.3v logic input supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot i nput esd protect i on human body model 2000 v electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v input mid voltage v mid 3.3 v +/-5% 1 1.8 v input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v input high current i ih v in = v dd -5 5 ua i il1 v in = 0 v; inputs with no pull-up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua operating supply current i dd3.3op full active, c l = full load; 350 ma all diff p airs driven 35 ma all differential p airs tri-stated 12 ma in p ut fre q uenc y 3 f i v dd = 3.3 v 14.31818 mhz 3 pin inductance 1 l pin 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 clk stabilization 1,2 t stab from v dd power-up or de- assertion of pd# to 1st clock 1.8 ms 1,2 modulation fre q uenc y trian g ular modulation 30 33 khz 1 tdrive_src src output enable after pci_sto p # de-assertion 15 ns 1 tdrive_pd# cpu output enable after pd# de-assertion 300 us 1 tfall_pd# pd# fall time of 5 ns 1 trise_pd# pd# rise time of 5 ns 2 tdrive_cpu_stop# cpu output enable after cpu_sto p # de-assertion 10 us 1 tfall_cpu_sto p # pd# fall time of 5 ns 1 trise_cpu_stop# pd# rise time of 5 ns 2 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 see timin g dia g rams for timin g re q uirements. i dd3.3pd 3 input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet pp m fre q uenc y accurac y on pll out p uts. input capacitance 1 input low current powerdown current
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 6 electrical characteristics - cpu & src 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 voltage high vhigh 660 850 1 voltage low vlow -150 150 1 max volta g evovs 1150 1 min volta g e vuds -300 1 crossin g volta g e ( abs ) vcross ( abs ) 250 550 mv 1 crossing voltage (var) d-vcross variation of crossin g over all ed g es 140 mv 1 lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 200mhz nominal 4.9985 5.0015 ns 2 200mhz s p read 4.9985 5.0266 ns 2 166.66mhz nominal 5.9982 6.0018 ns 2 166.66mhz s p read 5.9982 6.0320 ns 2 133.33mhz nominal 7.4978 7.5023 ns 2 133.33mhz s p read 7.4978 5.4000 ns 2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 200mhz nominal 4.8735 ns 1,2 166.66mhz nominal/s p read 5.8732 ns 1,2 133.33mhz nominal/s p read 7.3728 ns 1,2 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 skew t sk3 v t = 50% 100 ps 1 jitter, cycle to cycle t jcyc-cyc measurement from differential wavefrom 125 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. src clock outputs run at only 100mhz or 200mhz, specs for 133.33 and 166.66 do not apply to src clock pair. statistical measurement on single ended signal using oscilloscope math function. mv measurement on sin g le ended signal using absolute value. mv 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz tperiod average period absolute min period t absmin
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 7 electrical characteristics - 3v66 mode: 3v66 [4:0] t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 66.66mhz out p ut nominal 14.9955 15.0045 ns 2 66.66mhz out p ut s p read 14.9955 15.0799 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma ed g e rate risin g ed g e rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 250 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 250 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. clock period t period 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol electrical characteristics - pciclk/pciclk_f t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp msee t p eriod min-max values -300 300 pp m1,2 33.33mhz out p ut nominal 29.9910 30.0090 ns 2 33.33mhz out p ut s p read 29.9910 30.1598 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma edge rate rising edge rate 1 4 v/ns 1 ed g e rate fallin g ed g e rate 1 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t sk1 v t = 1.5 v 500 ps 1 jitter t jcyc-cyc v t = 1.5 v 3v66 250 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. clock period t period 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh output low current i ol
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 8 parameter symbol conditions min typ max units notes long accuracy ppm see tperiod min-max values -200 200 ppm 1,2 clock p eriod t p eriod 66.66mhz out p ut nominal 20.8257 20.8340 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @ min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma ed g e rate risin g ed g e rate 2 4 v/ns 1 edge rate falling edge rate 2 4 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1 ns 1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1 ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 long term jitter 125us period jitter (8khz frequency modulation am p litude ) 2ns1 1 guaranteed by design, not 100% tested in production. t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 5-10 pf (unless otherwise specified) electrical characteristics - 48mhz dot clock 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref out p ut is at 14.31818mhz output high current i oh output low current i ol
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 9 electrical characteristics - vch, 48mhz, usb t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units notes lon g accurac y pp msee t p eriod min-max values -200 200 pp m1,2 clock p eriod t p eriod 66.66mhz out p ut nominal 20.8257 20.8340 ns 2 output high voltage v oh i oh = -1 ma 2.4 v output low voltage v ol i ol = 1 ma 0.55 v v oh @ min = 1.0 v -33 ma v oh @ max = 3.135 v -33 ma v ol @min = 1.95 v 30 ma v ol @ max = 0.4 v 38 ma ed g e rate risin g ed g e rate 1 2 v/ns 1 edge rate falling edge rate 1 2 v/ns 1 rise time t r1 v ol = 0.4 v, v oh = 2.4 v 12ns1 fall time t f1 v oh = 2.4 v, v ol = 0.4 v 12ns1 duty cycle d t1 v t = 1.5 v 45 55 % 1 long term jitter 125us period jitter (8khz frequency modulation am p litude ) 6ns1 1 guaranteed b y desi g n, not 100% tested in p roduction. output low current i ol 2 all long term accuracy and clock period specifications are guaranteed with the assumption that ref output is at 14.31818mhz output high current i oh
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 10 electrical characteristics - ref-14.318mhz t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units long accuracy pp m 1 see tperiod min-max values -300 300 ppm clock period t period 14.318mhz output nominal 69.8270 69.8550 ns output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh @min = 1.0 v, v oh @max = 3.135 v -29 -23 ma output low current i ol 1 v ol @min = 1.95 v, v ol @max = 0.4 v 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 12ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 12ns skew t sk1 1 v t = 1.5 v 500 ps duty cycle d t1 1 v t = 1.5 v 45 55 % jitter t j c y c-c y c 1 v t = 1.5 v 1000 ps 1 guaranteed b y desi g n, not 100% tested in p roduction. group to group skews at common transition edges group symbol conditions min typ max units 200mhz cpu to 3v66 1 s cpu200-3v66 3v66 (4:0) leads 200mhz cpu -2.0 -1.5 -1.0 ns 3v66 to pci s 3v66-pci 3v66 (4:0) leads 33mhz pci 1.50 3.50 ns dot-usb s dot_usb 180 degrees out of phase 0.00 1.00 ns dot-vch s dot_vch in phase 0.00 1.00 ns 1. 3v66 mhz c l = 0pf, rseries = 33 ohm. cpu cl = 2 pf, rseries = 33 ohm, rshunt = 49.9 ohms. measured at the pins of the 932s208.
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 11 general i 2 c serial interface information for the ICS932S208 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 12 i 2 c table: read-back register pin # name control function t yp e0 1 pwd bit 7 reserved reserved - x bit 6 reserved reserved - x bit 5 reserved reserved - x bit 4 reserved reserved - x bit 3 reserved reserved - x bit 2 reserved reserved - x bit 1 fsb freq select 1 read back rx bit 0 fsa freq select 0 read back rx i 2 c table: spreading and device behavior control register pin # name control function t yp e0 1 pwd bit 7 src/src# src free-running control rw free-run stoppable 0 bit 6 src output control rw disable enable 1 bit 5 reserved reserved - x bit 4 reserved reserved - x bit 3 reserved reserved - x bit 2 cput2/cpuc2 output control rw disable enable 1 bit 1 cput1/cpuc1 output control rw disable enable 1 bit 0 cput0/cpuc0 output enable rw disable enable 1 i 2 c table: output control register pin # name control function t yp e0 1 pwd bit 7 src_pd# drive mode 0: driven in pd# rw driven hi-z 0 bit 6 src_stop# drive mode 0: driven in pci_stop# rw driven hi-z 0 bit 5 cput2_pd# drive mode rw driven hi-z 0 bit 4 cput1_pd# drive mode rw driven hi-z 0 bit 3 cput0_pd# drive mode rw driven hi-z 0 bit 2 reserved reserved - x bit 1 reserved reserved - x bit 0 reserved reserved - x 41, 40 - - - - 47, 46 47, 46 44, 43 38, 37 38, 37 - 44, 43 41, 40 b y te 2 38, 37 38, 37 - b y te 0 - - - reserved reserved - reserved - - - reserved 0:driven in pd# 1: tri-stated - reserved readback of cpu(3:0) frequency reserved b y te 1 reserved reserved reserved reserved reserved reserved
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 13 i 2 c table: output control register pin # name control function t yp e0 1 pwd bit 7 pci_stop# pci_stop# control 0:all stoppable pci are stopped rw enable disable 1 bit 6 pciclk6 output control rw disable enable 1 bit 5 pciclk5 out p ut control rw disable enable 1 bit 4 pciclk4 out p ut control rw disable enable 1 bit 3 pciclk3 out p ut control rw disable enable 1 bit 2 pciclk2 output control rw disable enable 1 bit 1 pciclk1 output control rw disable enable 1 bit 0 pciclk0 output control rw disable enable 1 i 2 c table: output control register pin # name control function t yp e0 1 pwd bit 7 48mhz_usb 2x output drive 0=2x drive rw 2x drive normal 1 bit 6 48mhz_usb output control rw disable enable 1 bit 5 pcif2 rw free-run stoppable 0 bit 4 pcif1 rw free-run stoppable 0 bit 3 pcif0 rw free-run stoppable 0 bit 2 pciclk_f2 output control rw disable enable 1 bit 1 pciclk_f1 output control rw disable enable 1 bit 0 pciclk_f0 output control rw disable enable 1 i 2 c table: output control register pin # name control function t yp e0 1 pwd bit 7 48mhz_dot output control rw disable enable 1 bit 6 cput3/cpuc3 output control rw disable enable 1 bit 5 3v66_4/vch select output select rw 3v66 vch 0 bit 4 3v66_4/vch output control rw disable enable 1 bit 3 3v66_3 output control rw disable enable 1 bit 2 3v66_2 output control rw disable enable 1 bit 1 3v66_1 output control rw disable enable 1 bit 0 3v66_0 output control rw disable enable 1 7 50/49 29 29 27 23 22 18 15 14 26 b y te 5 32 9 13 12 8 b y te 3 7,8,9,12,13,14,15, 18,19,20,37,38, 20 19 7 9 8 pci free-run ning control b y te 4 31 31
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 14 i 2 c table: output control and fix frequency register pin # name control function t yp e0 1 pwd bit 7 test clock mode test clock mode rw disable enable 0 bit 6 reserved - - - - 0 bit 5 fs testmode fs_a and fs_b operation rw normal test mode 0 bit 4 src100# src frequency select rw 100mhz 200mhz 0 bit 3 reserved - - - - 0 bit 2 ssen spread spectrum enable rw spread off spread on 0 bit 1 ref1 output control rw disable enable 1 bit 0 ref0 output control rw disable enable 1 i 2 c table: vendor & revision id register pin # name control function t yp e0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 - vendor id - - - b y te 7 - revision id - - - 1 37,38 7,8,9,12,13,14,15,1 8,19,20,22,23,26,27 ,29,31,32,37,38,40, 41,43,44,46,47 2 - 40,41,43,44,46,47 1,2,7,8,9,12,13,14, 15,18,19,20,22,23,2 6,27,29,31,32,37,38 ,40,41,43,44,46,47 b y te 6
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 15 the pci_stop# signal is on an active low input controlling pci and src outputs. if pcif (2:0) and src clocks can be set to be free-running through i2c programming. outputs set to be free-running will ignore both the pci_stop pin and the pci_stop register bit. pci stop functionality # p o t s _ i c pu p c# u p cc r s# c r s6 6 v 3i c p / f i c pt o d / b s uf e re t o n 1l a m r o nl a m r o nl a m r o nl a m r o nz h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1 0l a m r o nl a m r o n6 * f e r i t a o l f r o w o lz h m 6 6w o lz h m 8 4z h m 8 1 3 . 4 1 the clock samples the pci_stop# signal on a rising edge of pcif clock. after detecting the pci_stop# assertion low, all pci[6:0] and stoppable pcif[2:0] clocks will latch low on their next high to low transition. after the pci clocks are latched l ow, the src clock, (if set to stoppable) will latch high at iref * 6 (or tristate if byte 2 bit 6 = 1) upon its next low to high tr ansition and the src# will latch low as shown below. pci_stop# tsu pcif[2:0] 33mhz pci[6:0] 33mhz src 100mhz src# 100mhz pci_stop# assertion (transition from '1' to '0') the de-assertion of the pci_stop# signal is to be sampled on the rising edge of the pcif free running clock domain. after detecting pci_stop# de-assertion, all pci[6:0], stoppable pcif[2:0] and stoppable src clocks will resume in a glitch free manner. pci_stop# tsu tdrive_src pcif[2:0] 33mhz pci[6:0] 33mhz src 100mhz src# 100mhz pci_stop# - de-assertion
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 16 pd# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. when pd# is asserted low all clocks will be driven low before turning off the vco. in pd# de-assertion all clocks will start without glitches. pd#, power down # n w d r w pu p c# u p cc r s# c r s6 6 v 3i c p / f i c pt o d / b s uf e re t o n 1l a m r o nl a m r o nl a m r o nl a m r o nz h m 6 6z h m 3 3z h m 8 4z h m 8 1 3 . 4 1 0r o 2 * f e r i t a o l f t a o l f2 * f e r i t a o l f r o t a o l fw o lw o lw o lw o l notes: 1. refer to tristate control of cpu and src clocks in section 7.7 for tristate timing and operation. 2. refer to control registers in section 16 for cpu_stop, src_stop and pwrdwn smbus tristate control addresses. pd# should be sampled low by 2 consecutive cpu# rising edges before stopping clocks. all single ended clocks will be held low on their next high to low transition. all differential clocks will be held high on the next high to low transition of the complimentary clock. if the control registe r determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven. when the drive mode but corresponding to the cpu or src clock of interest is set to '0' the true clock will be driven high at 2 x iref and the complementary clock will be tristated. if the control register is programmed to '1' both clocks will be trista ted. pwrdwn# cpu, 133mhz cpu#, 133mhz src, 100mhz src#, 100mhz 3v66, 66mhz usb, 48mhz pci, 33mhz ref, 14.31818 pd# assertion
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 17 the time from the de-assertion of pd# or until power supply ramps to get stable clocks will be less than 1.8ms. if the drive mode control bit for pd# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of 200mv in less than 300 s of pd# deassertion. pwrdwn# tstable <1.8ms tdrive_pwrdwn# <300 s, >200mv cpu, 133mhz cpu#, 133mhz src, 100mhz src# 100mhz 3v66, 66mhz usb, 48mhz pci, 33mhz ref, 14.31818 pd# de-assertion the 3v66_4/vch pin can be configured to be a 66.66mhz modulated output or a non-spread 48mhz output. the default is 3v66 clock. the switching is controlled by byte 5 bit 5. if it is set to '1' this pin will output the 48mhz vch clock. the outp ut will go low on the falling edge of 3v66 for a minimum of 7.49ns. then the output will transition to 48mhz on the next rising edge of dot_48 clock. 3v66 3v66_4/vch dot_48 7.4 9 ns min 3v66_4/vch pin functionality
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 18 to minimize power consumption, cpu[2:0] clock outputs are individually configurable through smbus to be driven or tristated during pwrdwn# and cpu_stop# mode and the src clock is configurable to be driven or tristated during pci_stop# and pwrdwn# mode. each differential clock (src, cpu[2:0]) output can be disabled by setting the corresponding output's register oe bit to "0" (disable). disabled outputs are to be tristated regardless of "cpu_stop", "src_stop" and "pwrdwn" register bit settings. l a n g i s# d p n i pn i p # p o t s _ u p c p o t s _ u p c t i b e t a t s i r t n w d r w p t i b e t a t s i r t e l b a p p o t s - n o n s t u p t u o e l b a p p o t s s t u p t u o } 0 : 2 [ u p c11xx g n i n n u rg n i n n u r } 0 : 2 [ u p c10 0 xg n i n n u r6 x f e r i @ n e v i r d } 0 : 2 [ u p c101x g n i n n u re t a t s i r t } 0 : 2 [ u p c0xx0 2 x f e r i @ n e v i r d2 x f e r i @ n e v i r d } 0 : 2 [ u p c0xx1 e t a t s i r te t a t s i r t notes: 1. each output has four corresponding control register bits, oe, pwrdwn, cpu_stop and "free running" 2. iref x 6 and iref x 2 is the output current in the corresponding mode 3. see control registers section for bit address l a n g i s# d p n i pn i p # p o t s _ i c p p o t s _ i c p t i b e t a t s i r t n w d r w p t i b e t a t s i r t e l b a p p o t s - n o n t u p t u o e l b a p p o t s t u p t u o c r s11xx g n i n n u rg n i n n u r c r s10 0 xg n i n n u r6 x f e r i @ n e v i r d c r s101x g n i n n u re t a t s i r t c r s0xx0 2 x f e r i @ n e v i r d2 x f e r i @ n e v i r d c r s0xx1 e t a t s i r te t a t s i r t notes: 1. src output has four corresponding control register bits, oe, pwrdwn, src_stop and "free running" 2. iref x 6 and iref x 2 is the output current in the corresponding mode 3. see control registers section for bit address differential clock tristate
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 19 ordering information 932s208 y flnt min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a 0808 variations min max min max 56 18.31 18.55 .720 .730 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 n see variations see variations d mm. d (inch) symbol see variations see variations index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l example: designation for tape and reel packaging annealed lead free package type f = ssop revision designator (will not correlate with datasheet revision) device type xxxx y f ln t
idt tm programmable timing control hub tm for next gen p4 tm processor 0743g?01/26/10 ICS932S208 programmable timing control hub tm for next gen p4 tm processor 20 ordering information 932s208 y glnt min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c example: designation for tape and reel packaging annealed lead free package type g = tssop revision designator (will not correlate with datasheet revision) device type xxxx y g ln t
ICS932S208 programmable timing control hub tm for next gen p4 tm processor 21 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2009 integrated device technology , inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # f 12/2/2008 removed ics prefix from ordering information 12-20 g 1/26/2010 updated document template

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